Senior NoC Research Engineer (Network-on-Chip)

Senior NoC Research Engineer (Network-on-Chip) About SpiNNcloud

SpiNNcloud Systems is a pioneering deep-tech company developing brain inspired computing hardware and software based on the SpiNNaker2 technology. Our platform provides remote access to cutting-edge sparse computing resources, enabling breakthroughs in AI, HPC, and energy-efficient computing.

Role Overview

We are seeking a Senior Network-on-Chip (NoC) Research Engineer to shape the on-chip and chip-to-chip interconnect of SpiNNext, our next-generation chip. In systems built from very large numbers of cores, moving data efficiently determines both performance and energy efficiency. You will model, simulate and evaluate interconnect architectures under real ML workloads, and turn your findings into quantitative design decisions. You will report to our CTO and work closely with our chip architecture, hardware and software teams.

Key Responsibilities

Interconnect Architecture & Modelling

• Explore and evaluate NoC topologies, router and switch designs, arbitration, flow control, QoS and congestion control
• Build and maintain architectural models and simulations, using SST, gem5 or custom cycle-level and analytical models
• Develop traffic generators that reflect real ML workloads: collective communication, tensor parallelism and memory traffic

Performance Analysis & Design Trade-offs

• Analyse power, performance and area (PPA) trade-offs and back recommendations with quantitative evidence
• Ensure deadlock- and livelock-free designs through analysis, formal methods or simulation
• Investigate adaptive routing strategies and topology options

Protocols, IP & Scale-out

• Translate complex protocol and IP specifications (AXI, CHI, APB) into clear design requirements
• Evaluate third-party interconnect IP and support build-versus-buy decisions
• Assess how RDMA concepts and chip-to-chip interfaces shape data movement between accelerators at system scale

Research & Collaboration

• Present findings and recommendations to architecture and leadership teams
• Contribute to publications and patents in on-chip networks and data movement for ML

Required Qualifications

Education & Experience

• PhD, or Master's with equivalent research experience, in Electrical Engineering, Computer Engineering, Computer Science or a related field
• Senior-level track record in NoC or interconnect architecture, in industry or applied research

Technical Skills

• Strong background in on-chip interconnect and traffic management: NoC topologies, routers and switches, arbitration, flow control, QoS and congestion control
• Good understanding of ML workloads and accelerator architectures, including how collective communication, tensor parallelism and memory traffic stress the interconnect
• Working knowledge of on-chip protocols such as AXI, CHI or AHB
• Understanding of RDMA concepts and transports (InfiniBand, RoCE), including queue pairs, memory registration and zero-copy transfers
• Experience reasoning about PPA trade-offs with quantitative evidence
• Hands-on architectural modelling and simulation (SST, gem5 or own models), with strong Python and C++
• Ability to read complex protocol and IP specifications and turn them into clear design requirements
• Experience with deadlock and livelock avoidance, adaptive routing or topology exploration
• Clear written and verbal communication in English, and a proactive, collaborative approach to open-ended problems

Preferred Qualifications

• Experience with chip-to-chip and die-to-die interfaces such as PCIe, Ethernet or UCIe
• Experience with memory subsystems such as HBM and CXL
• Publications or patents in on-chip networks, interconnect architecture, or data movement for ML or HPC
• Familiarity with massively parallel architectures

What We Offer

• Competitive salary based on experience
• 30 days annual vacation, up to 2 weeks of work abroad
• Work on cutting-edge sparse computing technology
• High-impact role with direct influence on the architecture of SpiNNext
• Collaborative team culture with experienced engineers from academia and industry
• Equity participation in a growing deep-tech company

How to Apply

Please include:

• CV highlighting relevant interconnect, NoC or architecture research experience
• Brief cover letter describing an interconnect or data-movement problem you analysed and what you recommended
• Links to publications, patents or public code (optional)
• Salary expectations and earliest start date
• Your current location, and whether you would need visa sponsorship and/or relocation support to work in Germany.

SpiNNcloud Systems is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We encourage applications from candidates of all backgrounds, regardless of race, gender, age, disability, sexual orientation, or national origin.